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Complete UVM TB For Verification Of Adder
RISC-V Tools (ISA Simulator and Tests)
Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Human Activity Recognition example using TensorFlow on smartphone sensors dataset and an LSTM RNN. Classifying the type of movement amongst six activity categories - Guillaume Chevalier
hardware security course from Coursera and University of Maryland
Trojan Hardware implemented in the OpenCores Amber ARM Core
Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security
Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security
Apply Fully Homomorphic Encryption Scheme (FHE) to hardware to ensure hardware security against Hardware Trojan Horse.
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
Fork of https://code.google.com/archive/p/ipv6-hosts/, focusing on automation
embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC
OpenThread released by Google is an open-source implementation of the Thread networking protocol
Repository containing releases of prebuilt GNU toolchains for DesignWare ARC Processors from Synopsys (available from "releases" link below).