Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit

Visualize your systemd logs with filters, themes... built on Rust & Vue

UVM register model course

Parse .brd files generated by Allegro

C preprocessor tricks, explained

Ссылки к видео

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

PCIe (1.0a to 2.0) Virtual host model for verilog

UVM agents

z - jump around

Convert PDF to markdown quickly with high accuracy

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Статья про применение фильтров в GTKWave

uvm AXI BFM(bus functional model)

Explain complex systems using visuals and simple terms. Help you prepare for system design interviews.

Emacs configuration for authors who research, write and publish articles, books and websites.

Library containing various VHDL IPs

Structured UVM Course

Python Tool for UVM Testbench Generation

A verilog implementation of an aynchronous FIFO (First In First Out).

Avalon-MM SPI bridge

The Linux Kernel Module Programming Guide (updated for 5.0+ kernels)

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Code used in

Wavedrom Major Mode for Emacs

Example based guide for text processing with Perl from the command line

UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)