This project implements a 5 stage pipeline with solution to data hazard and control hazard. The supported mips instructions are
Data transfer instructions:
- lw, sw
Arithmetic instructions:
- add, addu, addi, addiu, sub, subu
Logical instructions
- and, andi, nor, or, ori, xor, xori
Shifting instructions
- sll, sllv, srl, srlv, sra, srav Branch/Jump instructions:
- beq, bne, slt
- j, jr, jal