undergraduate @ Yao Class, IIIS, Tsinghua University
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Tsinghua University
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Network-on-Chip-Verilog
Network-on-Chip-Verilog PublicA 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.
VHDL 5
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rCore-Tutorial-Code-2023S
rCore-Tutorial-Code-2023S Public templateForked from LearningOS/rCore-Tutorial-Code-2023S
My implementation of rCore. Check each branch for details!
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scalable-image-server
scalable-image-server PublicProject 1 Part 1 for Operating Systems and Distributed Systems, IIIS, Tsinghua University, 2023 Fall
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