The Risc-V ISA has an optional "V" extension for vector support. This patch
introduces vector accelerated routines for the following methods:
 + local_lpc_compute_autocorrelation
 + local_lpc_compute_residual_from_qlp_coefficients

This patch disables building with Risc-V Vector support. It can be enabled
using `--enable-riscv-vector-optimizations` in autotools or `-DRISCV_VECTOR=ON`
using cmake.

Building with vector support is disabled by default because the patch was tested
only on QEMU for now for correctness.

Limitations:
 + RiscV vector support is limited to very modern compilers (Clang 16 or later)
   for the time being
 + The width of each vector element on Risc-V is configurable by the silicon
   vendor. This patch assumes a reasonable width of at least 128 bits per vector
   register for now.

Future Work:
 + Only local_lpc_compute_residual_from_qlp_coefficients has been optimized for
   now and the implementation was based heavily on the Intel AVX implementation.
   There is likely a more idiomatic Risc-V implementation that is feasible.

This patch dynamically detects whether the RiscV vector unit
is available and only enables the intrinsic routines if it is.

Tested by launching QEMU with the Vector Extensions enabled
and disabled and observed that the intrinsic routines were
only patched in when vector was enabled.

This was causing a build failure if riscv_vector was not available
on the system.

When detecting "riscv_vector.h" using autotools and cmake,
invoke the toolchain with -march=rv64gcv.