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Implement core1 #112

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190cba8
Implement TBMAN
mingpepe Nov 28, 2022
de3601f
Implement REF/SYS CTRL & SELECT for clock
mingpepe Nov 28, 2022
e7a222c
Define enum for cores
mingpepe Dec 12, 2022
dfbeaf0
Add API for peripheral to read from core
mingpepe Dec 12, 2022
aca3a9c
Define onSEV event to wakeup another core
mingpepe Dec 12, 2022
1b660e3
Define onBreak event for GDB
mingpepe Dec 12, 2022
c64c141
Implement read/write via core for ppb
mingpepe Dec 12, 2022
d5a1074
Implement FIFO registers in SIO
mingpepe Dec 12, 2022
a31e8fc
Define 2 cores in rp2040
mingpepe Dec 12, 2022
dc29d0c
Register onSEV event for each core
mingpepe Dec 12, 2022
efb7820
Implement NMI_MASK for syscfg
mingpepe Dec 12, 2022
dcc32ab
Modify debugger to debug only on core0
mingpepe Dec 12, 2022
26fb63f
Update unit test
mingpepe Dec 12, 2022
9b54d9d
Update test-utils
mingpepe Dec 12, 2022
b1b4560
Update demo code
mingpepe Dec 12, 2022
d12a4b5
Merge branch 'master' into core1
mingpepe Dec 12, 2022
4a0cf99
Let each core has its divider
mingpepe Dec 13, 2022
10ec3e6
Let each core has its interpolator
mingpepe Dec 13, 2022
fd563cd
Move fifo related logic to each core
mingpepe Dec 13, 2022
c9ab5ea
Do no need to pass core info to each core
mingpepe Dec 13, 2022
6f2da85
Add core info to warning message
mingpepe Dec 13, 2022
278bda7
Execute core0 and core1 interleaving
mingpepe Jan 30, 2023
26f77aa
Merge branch 'master' into core1
mingpepe Feb 6, 2023
1290137
Fix wrong merge
mingpepe Feb 6, 2023
9b55ad5
Run lint
mingpepe Feb 6, 2023
9bb7e7a
Fix error by lint
mingpepe Feb 6, 2023
23bf9d3
Rename variable
mingpepe Mar 21, 2023
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Implement REF/SYS CTRL & SELECT for clock
  • Loading branch information
mingpepe committed Nov 28, 2022
commit de3601f592ec40f7681f02769b5d2be187236c3b
27 changes: 24 additions & 3 deletions src/peripherals/clocks.ts
Original file line number Diff line number Diff line change
@@ -1,22 +1,43 @@
import { RP2040 } from '../rp2040';
import { BasePeripheral, Peripheral } from './peripheral';

const CLK_REF_CTRL = 0x30;
const CLK_REF_SELECTED = 0x38;
const CLK_SYS_CTRL = 0x3c;
const CLK_SYS_SELECTED = 0x44;

export class RPClocks extends BasePeripheral implements Peripheral {
refCtrl = 0;
sysCtrl = 0;
constructor(rp2040: RP2040, name: string) {
super(rp2040, name);
}

readUint32(offset: number) {
switch (offset) {
case CLK_REF_CTRL:
return this.refCtrl;
case CLK_REF_SELECTED:
return 1;

return 1 << (this.refCtrl & 0x03);
case CLK_SYS_CTRL:
return this.sysCtrl;
case CLK_SYS_SELECTED:
return 1;
return 1 << (this.sysCtrl & 0x01);
}
return super.readUint32(offset);
}

writeUint32(offset: number, value: number): void {
switch (offset) {
case CLK_REF_CTRL:
this.refCtrl = value;
break;
case CLK_SYS_CTRL:
this.sysCtrl = value;
break;
default:
super.writeUint32(offset, value);
break;
}
}
}