Added filter files for gtkwave in demo2 and demo3

README.md

@@ -46,14 +46,17 @@ with Icestorm tools (at least) setting memory to 256 bytes and the trigger posit
 6. Write your verilog in the project directory.
 7. Create a top_of_verifla module. Here are the signals:
 * clk - Clock
-* cqual - Qualifier for data capture clock (UART and other things use clk alone). If you don't want a qualifer, just set to 1'b1. IMPORTANT: You do need to set this to something.
+* cqual - Qualifier for data capture clock (UART and other things use clk alone). If you don't want a qualifer, just set to 1'b1 (which is the default).
 * rst_l - Active low reset.
 * sys_run - High to arm logic analyzer. If you only want to arm from the PC, set to 1'b0.
 * data_in - Your inputs. Group together like {led3, led2, led1, led0, count[3:0]}.
 * uart_XMIT_dataH - Your RS232 transmit line
 * uart_REC_dataH - Your RS232 receive line
 * armed - digital output showing LA is armed
 * triggered - digital output showing LA is triggered
+* trigqual - Must be set to 1 to allow internal trigger to occur (default is 1)
+* exttrig - Set to 1 to force a trigger (default is 0; does not respect trigqual)
+
 8. Once running you can use the original Java program to create a .v file you will need to simulate or the C program (la2vcd) to create a .vcd you can read using a waveform viewer (like GTKWave)
 
 # Notes about using GTKWave

demos/ice40/demo2/demo2.gtkw

@@ -1,19 +1,19 @@
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Mon Aug 27 05:33:17 2018
+[*] Tue Aug 28 05:45:28 2018
 [*]
 [dumpfile] "/home/alw/fpga/verifla/demos/ice40/demo2/demo2.vcd"
-[dumpfile_mtime] "Mon Aug 27 05:30:17 2018"
-[dumpfile_size] 16279
+[dumpfile_mtime] "Tue Aug 28 04:59:29 2018"
+[dumpfile_size] 1267972
 [savefile] "/home/alw/fpga/verifla/demos/ice40/demo2/demo2.gtkw"
 [timestart] 0
-[size] 1919 1021
-[pos] 1908 -1
-*-16.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[size] 1897 2113
+[pos] -1 -1
+*-28.000000 693000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [sst_width] 310
 [signals_width] 186
 [sst_expanded] 1
-[sst_vpaned_height] 274
+[sst_vpaned_height] 272
 @28
 CAPTURE.clk
 CAPTURE.triggered
@@ -43,13 +43,14 @@ CAPTURE.capdata[15:0]
 -group_end
 @28
 +{led1} (12)CAPTURE.capdata[15:0]
-@c00028
+@c02029
+^1 /home/alw/fpga/verifla/demos/ice40/demo2/gtkwavefilter.txt
 #{state} (13)CAPTURE.capdata[15:0] (14)CAPTURE.capdata[15:0] (15)CAPTURE.capdata[15:0]
 @28
 (13)CAPTURE.capdata[15:0]
 (14)CAPTURE.capdata[15:0]
 (15)CAPTURE.capdata[15:0]
-@1401200
+@1401209
 -group_end
 @1001200
 -group_end

demos/ice40/demo2/gtkwavefilter.txt

@@ -0,0 +1,3 @@
+001 WAIT0
+010 WAIT1
+100 WAIT2

demos/ice40/demo3/gtkwavefilter.txt

@@ -0,0 +1,5 @@
+00 CW
+01 CWAIT
+10 CCW
+11 CCWAIT
+

demos/ice40/demo3/spin.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Mon Aug 27 05:28:01 2018
+[*] Tue Aug 28 05:48:33 2018
 [*]
 [dumpfile] "/home/alw/fpga/verifla/demos/ice40/demo3/spin.vcd"
-[dumpfile_mtime] "Mon Aug 27 05:26:04 2018"
-[dumpfile_size] 426017219
+[dumpfile_mtime] "Tue Aug 28 05:18:37 2018"
+[dumpfile_size] 319757518
 [savefile] "/home/alw/fpga/verifla/demos/ice40/demo3/spin.gtkw"
-[timestart] 2320000000
-[size] 1897 2113
+[timestart] 79530000000
+[size] 3828 2113
 [pos] -1 -1
-*-32.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-34.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [sst_width] 310
 [signals_width] 186
 [sst_expanded] 1
@@ -32,12 +32,13 @@ CAPTURE.capdata[15:0]
 (7)CAPTURE.capdata[15:0]
 @1401200
 -group_end
-@c00028
+@c02029
+^1 /home/alw/fpga/verifla/demos/ice40/demo3/gtkwavefilter.txt
 #{state} (14)CAPTURE.capdata[15:0] (15)CAPTURE.capdata[15:0]
 @28
 (14)CAPTURE.capdata[15:0]
 (15)CAPTURE.capdata[15:0]
-@1401200
+@1401201
 -group_end
 @1001200
 -group_end