Tested in 1920x1080@120Hz mode with Digilent Genesys-2 Board Fpga test based on Will Green's Verilog code This code also avaliable on GitHub: projf project

Project structure

HW - schematic and design files (BOM, Gerbers ...)

HDL - Double link 1920x1080@120Hz mode test design Verilog source files for Genesys-2 Demo Board