Pinned Loading

1. Cadence-Inverter-Design-Behavioral-Post-Layout-Simulation-DRC-LVS Cadence-Inverter-Design-Behavioral-Post-Layout-Simulation-DRC-LVS Public

   This repository showcases an optimized inverter design process in Cadence Virtuoso. It includes behavioral simulations, post-layout simulations, layout verification with DRC/LVS.

   SourcePawn

2. FIFO FIFO Public

   RTL design of a Single clock and Dual Clock FIFO.

   Verilog

3. N_Bit_Multiplier N_Bit_Multiplier Public

   A versatile Verilog implementation of an N-bit multiplier with Binary-Coded Decimal (BCD) conversion, ready for deployment on Xilinx FPGAs.

   Verilog

4. obstacle_detection_using_ultrasonic_sensor obstacle_detection_using_ultrasonic_sensor Public

   C++ 1

5. Customer-behaviour-using-linear-regression- Customer-behaviour-using-linear-regression- Public

   Jupyter Notebook

6. Analog-Lab-Report- Analog-Lab-Report- Public

   Analog Lab Report