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Specification of the Wishbone SoC Interconnect Architecture

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The Wishbone SoC Interconnect Architecture

Wishbone is an interconnect for Systems-on-Chip. It's been placed in the public domain and is (as far as we know) free from patents and royalties. Wishbone is widely used in free and open source designs, but it can also be used in commercial designs without limitations.

Specification Documents

Today, the most used versions of Wishbone are revision B.3, and to a lesser extend, revision B.4. Revision B.4 most notably adds support for pipelining more efficient access to high-latency peripherals like DRAM.

Note: Version B.4 adds new features which are not as widely accepted as the functionality of the previous versions. A future version of the specification will try to reach wider agreement in this regard.

Superseeded Specifications

The following specification documents have been replaced by newer versions and should not be used for new designs any more.

Application Notes

Contributing and Maintainership

The primary author and maintainer of the Wishbone specification is Richard Herveille. The specification is now maintained by a group of people under the umbrella of the FOSSi Foundation. Please join the [email protected] mailing list (subscribe) if you have questions or want to contribute to the specification process.

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Specification of the Wishbone SoC Interconnect Architecture

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