Submission template for Tiny Tapeout 8 - Verilog HDL Projects

SystemVerilog compiler and language services

find all circuits of a directed graph using johnson's algorithm and java implementation by frank meyer

Converts the SystemRDL data into pdf Register specification

Verilator open-source SystemVerilog simulator and lint system

SystemRDL 2.0 language compiler front-end

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Bus Pirate 5 Firmware Documentation

ESP32/8266 Arduino as (X)SVF JTAG programmer

VHDL generator from SystemRDL

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A handy phone call manager with phonebook, number blocking and multi-SIM support

Starter Verilog project for VGA games on DE10 lite

inversecsg code from paper https://dl.acm.org/citation.cfm?id=3275006 adapted to generate node-occ-csg-editor code

Icarus Verilog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

T9 English IME input for Android using hardware keypad. (e.g. SoftBank 007SH)

Private, cross-platform package tracking app

Yet Another Parametric Projectbox Box

Proof-of-concept for OpenSCAD step file importing