Discussions

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  ASAP7 Synthesis using OpenROAD Yosys.

  nerdylye asked Jul 26, 2023 in Q&A · Closed · Unanswered

  

  

  

  

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  build-setup error

  danielfufu asked Jul 6, 2024 in Q&A · Unanswered

  

  

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  Sky130-OpenRoad Tutorial Place and Route Fail

  johnw08 asked Apr 18, 2024 in Q&A · Answered

  

  

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  How to generate axi 128-bit width for memory and mmio bus?

  thabner asked Mar 25, 2024 in Q&A · Unanswered

  

  

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  Faster build for only changed module

  HazemAlindari asked Mar 21, 2024 in Q&A · Closed · Answered

  

  

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  Is asm volatile ("csrr %0, mhartid" : "=r"(hartid)); only allowed inside Verilator/VCS simulation?

  JL102 asked Oct 17, 2023 in Q&A · Unanswered

  

  

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  Scala metals with vim

  gonsolo started Feb 6, 2024 in General

  

  

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  Problems with ./build-setup.sh and conda

  oharboe started Dec 13, 2023 in General · Closed

  

  

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  Problem when set IP address for FPGA board

  phlong722 asked Jan 25, 2024 in Q&A · Unanswered

  

  

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  Why is ron_out.valid dependent on io.resp.ready?

  JL102 asked Nov 7, 2023 in Q&A · Unanswered

  

  

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  Constellation: Messages arrive out-of-order if I slam the NoC with lots of messages

  JL102 asked Oct 17, 2023 in Q&A · Answered

  

  

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  when connecting the cores of the SOC with TLNOC

  yulilicao asked Sep 4, 2023 in Q&A · Unanswered

  

  

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  What is the granularity of atomic operations under Tilelink?

  OrkunAliOzkan asked Aug 24, 2023 in Q&A · Unanswered

  

  

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  Internship or hourly position for building an AI accelerator targeted for space hardware

  leochand101 started Aug 23, 2023 in General

  

  

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  Adding I2C and SPI flash to Design

  clikbait295 asked Jul 31, 2023 in Q&A · Unanswered

  

  

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  Regarding: Config with private scratchpad, independent data load and shared scratchpad bank as mail box.

  ashuthosh-mr asked Aug 3, 2023 in Q&A · Unanswered

  

  

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  How does the system bus connect modules together?

  OrkunAliOzkan asked Aug 1, 2023 in Q&A · Unanswered

  

  

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  Can I use Chipyard FPGA flow with the Xilinx ZYNQ ZC706 board?

  sammy17 asked May 15, 2023 in Q&A · Unanswered

  

  

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  Why source.ready := ingress.flit.ready && beat === 1.U ?

  JL102 asked Jul 10, 2023 in Q&A · Answered

  

  

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  Which repo should I write this bug for? (error when compiling firrtl: error: 'module' must be first token on its line)

  JL102 asked Jul 3, 2023 in Q&A · Answered

  

  

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  What is the reason to uniquify the module names?

  davidmlw started Jun 22, 2023 in General · Closed

  

  

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  Submit a Talk to the First FireSim and Chipyard User/Developer Workshop @ ASPLOS 2023!

  sagark announced Jan 31, 2023 in Announcements

  

  

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