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1. Intra-task-DVFS-simulator Intra-task-DVFS-simulator Public

   A cycle-accurate simulator for hard real-time system for my master thesis. It perform Intra-task DVFS behaviour within execution of periodic tasks aiming at reducing response time jitter and energy…

   C++

2. MulticoreCache_sim MulticoreCache_sim Public

   A simple simulator for evaluating the hit/miss ratio of L1 data cache under multicore system with one main memory.

   C++

3. QC_LDPC_Construction_Optimisation QC_LDPC_Construction_Optimisation Public

   A framework of constructing Quasi-Cyclic LDPC Codes using some optimisation approaches.

   C++ 1

4. IB_layerLDPC_asymAccess_memShare IB_layerLDPC_asymAccess_memShare Public

   Enhancement of InformationBottleneck Implementation on FPGAs

   Verilog 1

5. UART_RTL_UVM UART_RTL_UVM Public

   This is a simple exercise of UART transceiver's RTL design along with UVM-based verification

   SystemVerilog

6. Generic_SRAM_APB Generic_SRAM_APB Public

   RTL design of a generic SRAM module with APB I/F.

   SystemVerilog