- 👋 Hi, I’m 吳華楨, a master student in the National Yang Ming Chiao Tung University (NYCU).
- 👀 I’m majoring in Computer Science and Digital Integrated Circuits Design.
- 🌱 I’m currently learning AI model analysis, software hardware co-design and digital circuit design in EIS Lab(嵌入式智慧系統實驗室) of NYCU. My advising professor is Professor Chun-Jen Tsai(蔡淳仁). Details of my implementation labs and projects can be found at https://github.com/trista-csee
- 💞️ The research field of my master's degree is AI hardware accelerator.
- 📫 How to reach me at [email protected]
🎯
Focusing
Precisely because I understand that I have nothing, I record what I learn to help those in need.
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National Yang Ming Chiao Tung University
- Taiwan
- in/hua-chen-wu-363252241
Pinned Loading
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Asynchronous_FIFO
Asynchronous_FIFO PublicDesign an asynchronous FIFO to safely pass data from one clock domain to another asynchronous clock domain
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Round_Robin_Arbiter
Round_Robin_Arbiter PublicDesign a round-robin arbiter to ensure that each request has an equal chance of being granted access to shared resources.
SystemVerilog 1
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Pipeline_Optimized_Carry_Look_Ahead_Adder
Pipeline_Optimized_Carry_Look_Ahead_Adder PublicDesign a pipeline and high-performance carry-look-ahead adder and verify using automated comparison testbench
Verilog 1
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Nbit_Bidirectional_Shift_Register
Nbit_Bidirectional_Shift_Register PublicDesig a bidirectional shift register with parameterized width
Verilog 1
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Parking_System_Moore_Machine
Parking_System_Moore_Machine PublicDesign a parking system that can verify the password and control the gate when the entrance and exit sensors detect an approaching vehicle
Verilog 1
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Traffic_Light_Controller_Mealy_Machine
Traffic_Light_Controller_Mealy_Machine PublicDesigning a traffic light controller to coordinate traffic lights on highways and farm ways
Verilog 1
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