write-back

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yadav-sachin / Multilevel-Cache-Controller

Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy. Implemented on a Basys3 Artix-7 FPGA with proper delays and hit signals.

cache-control lru-cache write-back basys3-fpga set-associative-cache four-way-set-associative

Updated Jul 22, 2020
Verilog

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write-back

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yadav-sachin / Multilevel-Cache-Controller

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