abdelazeem201 / ORCA Star 12 Code Issues Pull requests Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology asic vhdl rtl verilog synthesis synopsys hdl fpga-soc pnr upf asic-design synopsys-vcs synopsys-dc systemonchip synopsys-iccii saed32nm Updated Sep 10, 2023 Verilog
OpenEDF / verilog-basic Star 10 Code Issues Pull requests learn the combinational and sequential logic circuit. simulator fpga simulation vhdl verilog iverilog ice40up5k fpga-programming synopsys-vcs synopsys-dc Updated Oct 2, 2024 SystemVerilog
tatan432 / AES_ENCODER Star 8 Code Issues Pull requests RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC. digital rtl aes-128 synthesis aes-encryption digital-design verilog-project encription synopsys-vcs synopsys-dc ee4415 Updated Dec 11, 2020 Verilog
vb000 / vcs-slave-mode Star 4 Code Issues Pull requests Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv). verilog-simulator shared-object synopsys-vcs Updated Mar 5, 2020 Makefile