Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
fpga
hls
accelerator
architecture
vlsi
high-level-synthesis
stencils
vivado-hls
stencil-computations
vitis-hls
-
Updated
Sep 13, 2022 - C++
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
OpenACC GPU parallelization for various numerical methods and miscellaneous problems using FORTRAN
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
OpenACC GPU parallelization for various numerical methods and miscellaneous problems using C
An Application-Specific Memory Subsystem Benchmarking Framework
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