mixed-signal
Here are 27 public repositories matching this topic...
Fast, interactive Julia/GTK+ plots (+Smith charts +Gtk widget +Cairo-only images)
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Aug 5, 2024 - Julia
Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
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Jul 30, 2024 - Verilog
Automatic generation of real number models from analog circuits
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Apr 2, 2024 - Python
VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
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Jan 4, 2022 - Verilog
Open Source PHY v2
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Apr 25, 2024 - SystemVerilog
HSPICE and MATLAB simulation files of a tracking SAR ADC
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Jun 29, 2024 - MATLAB
A low noise nanovoltmeter design files and code
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May 22, 2024 - C
Raspberry Pi powered High Altitude Weather Balloon
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Jul 31, 2020 - HTML
gnucap mirror, defunct, moved to codeberg.org/gnucap
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Aug 6, 2020 - C++
Pure Python async code for talking to the BitScope micro
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Aug 9, 2021 - Python
Code for "Improving Noise Tolerance of Mixed-Signal Neural Networks" https://arxiv.org/abs/1904.01705
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Feb 12, 2022 - Python
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
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May 31, 2022 - Verilog
A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence
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Jun 2, 2022
This repository contains the files (schematic, test bench, simulation results) from the course Mixed-Signal Design(undergrad)
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Jan 3, 2022
3bit digitally controlled PWM Generator using eSim, using ngveri(Makerchip) and ngspice
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Jun 18, 2022 - Verilog
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
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Dec 31, 2021 - Tcl
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
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Sep 24, 2022 - Verilog
Notes along the way...
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Nov 5, 2019
Mixed signal PCB with op-amps, filters, ADC/DAC interfaces. ADACUS
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Aug 19, 2024
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