IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
-
Updated
Jul 31, 2024 - Python
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
Rsyn – An Extensible Physical Synthesis Framework
Development repository for ViennaPS, a fully-fledged semiconductor fabrication process simulation library.
Simple UVM phase jumping
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
Julia port of Prof. Boris Murmann's gm/ID Starter Kit https://web.stanford.edu/~murmann/gmid
Implementation of 2-bit & 8-bit CMOS microelectronic circuit simulations in HSpice
Exercício 02 de SystemVerilog
Python-based electronic design automation (EDA) tool for characterizing digital standard cells designed in SKY130 PDK. The characterization process is based in the Synopsys Liberty User Guides and Reference Manual Suite - Version 2017.06
Repository for open-source tools to VLSI design
A universal device that allows improving modern traffic lights and adapting them for people with disabilities.
Execício 1 de SystemVerilog
The Internet of Stranger Things (IoST) is an IoT project using the Blynk service, the Arduino compatible Adafruit Feather WiFi board, and WS2811 individually programmable LEDs. Other optional components are included in this particular build of the project that do not effect its overall functionality. Such items will be described within the sourc…
Project made in Introduction to Microelectronics class
AVR's ATMega328P in chip form with castellated pins
Simulating ADC background calibration algorithms in OpenCL
Python I2C driver for 3rd party ST LPS22 pressure sensor
A tool for matching devices in analog layout
A repository for embedded systems learning portals
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
Add a description, image, and links to the microelectronics topic page so that developers can more easily learn about it.
To associate your repository with the microelectronics topic, visit your repo's landing page and select "manage topics."