Opensource DDR3 Controller
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Updated
Jul 15, 2024 - Verilog
Opensource DDR3 Controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
mirror of https://git.elphel.com/Elphel/eddr3
🛠 A SDRAM controller in Verilog HDL
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
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