sdnellen / open-register-design-tool Star 15 Code Issues Pull requests Tool to generate register RTL, models, and docs using SystemRDL or JSpec input eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design Updated Jan 31, 2024 Verilog
firesim / aws-fpga-firesim Star 11 Code Issues Pull requests AWS Shell for FireSim fpga aws-ec2 fpga-development aws-fpga Updated Jun 5, 2024 VHDL
arnav-gudibande / fpga-intro-guide Star 4 Code Issues Pull requests Introductory guide to building and programming FPGAs fpga hdl modelsim quartus-prime quartus fpga-development Updated Aug 3, 2017 Tcl
alexeykosinov / UT8QNF8M8-Controller Star 2 Code Issues Pull requests UT8QNF8M8 NOR Flash Controller VHDL Module vhdl fpga-firmware fpga-development aeroflex ut8qnf8m8 nor-flash Updated Jan 14, 2019 VHDL
Strato75 / FPGACorrelator Star 2 Code Issues Pull requests FPGA backend correlator for the microwave holography system installed on the Sardinia Radio Telescope (SRT) python fpga backend verilog srt radioastronomy sardinia fpga-development correlator sardinia-radio-telescope microwave-holography Updated Mar 26, 2020 Verilog
KarimZakzouk / AES Star 0 Code Issues Pull requests Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms. security cryptography fpga aes-256 aes-128 aes-192 aes-encryption verilog-hdl data-encryption data-security advanced-encryption-standard aes-decryption fpga-development algorithm-implementation hardware-design Updated May 14, 2024 Verilog