Toolset to capture, simulate, synthesize and verify graph models
fsm
async
simulation
eda
cad
petri-nets
circuit
formal-verification
logic-synthesis
stg
formal-specification
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Updated
Jul 4, 2024 - Java
Toolset to capture, simulate, synthesize and verify graph models
Design by contract extension to Java using annotations and bytecode injection
My third year University dissertation, Term Rewriting System
Specification and formal verification of traffic light control system.
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