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📡 In this project, we only focus on the Multi-Slave Regular Mode. We design and implement the following components of the SPI modules using Verilog such that they match the requirements of the development testbench and match the SPI specifications (Master - Slave - Self-Checking Testbenches for the Master and Slave)
🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.