PashaBarahimi / Digital-Logic-Design-Lab-Experiments Star 4 Code Issues Pull requests Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers. fpga radix-4 function-generator baud-rate digital-logic-design clock-generator digital-logic-design-lab Updated Aug 3, 2022 Verilog
mohadeseh-ghafoori / FPGA-Lab Star 2 Code Issues Pull requests codes of my IUT FPGA LAB state-machine image-processing primitives verilog uart usart fifo median-filter microblaze baud-rate ft2232 sobel-filter matlabsimulink Updated Nov 1, 2022 Verilog
MisaghM / Digital-Logic-Design-Lab-Experiments Star 1 Code Issues Pull requests Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers. fpga radix-4 function-generator baud-rate digital-logic-design clock-generator digital-logic-design-lab Updated Aug 3, 2022 Verilog