i2c signal bypass fpga

Open Logic HDL Standard Library

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Hardware Description Language Translator

All the mumbo jumbo code that is me learning VHDL. Primarily targeted for Microsemi Smartfusion2

A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.

Guidelines for low-level cryptography software

A minimal GPU design in Verilog to learn how GPUs work from the ground up

A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Low-cost PCIe x1 to SMA adapter

The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the FPGA can be monitored in a waveform.

Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020

Reads a state transition system and performs property checking

SystemVerilog synthesis tool

RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga

Ada-language framework

Directly Synthesized Content-Addressable Memory (DSCAM) is an innovative method to implement very large CAMs on FPGAs. DSCAM offers guaranteed low-latency and high throughput lookups with an afford…

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

Python/C/RTL cosimulation with Xilinx's xsim simulator

A community-supported supercharged version of paperless: scan, index and archive all your physical documents

WIP 100BASE-TX PHY

OSVVM submodule for Co-simulation features

Mirror of Lauterbach's JSwitch VHDL IP

GNU Make Standard Library

Do-It-Yourself PID für Espressomaschinen

Formal verification (experiments) targeting the NEORV32 RISC-V processor.

This is the Rust course used by the Android team at Google. It provides you the material to quickly teach Rust.