5.2 Driver Initializing Steps

###1. if the internal PHY is required open, the following steps are to activate it:

set GPCR (REG_1E) GEP_CNTL0 bit[0]=1
set GPR (REG_1F) GEPIO0 bit[0]=0

The default status of the DM9000 is to power down the internal PHY by the value GEPIO0=1. Since the internal PHY have been powered down, the wakeup procedure will be needed to enable it. Please refer to the section 3.4 about the GPIO settings.

###2. do the software reset twice to initial DM9000:

set NCR (REG_00) bit[2:0]=011 for a period time, at least 20 us.
clear NCR (REG_00) bit[2:0]=000

issue 2nd reset

set NCR (REG_00) bit[2:0]=011 for a period time, at least 20 us.
clear NCR (REG_00) bit[2:0]=000

###3. program the NCR register.

Choose normal mode

set NCR (REG_00) LBK bit[2:1]=00

The system designer can choose the network operations such as setting the internal/ external PHY, the full/ half duplex mode, the loop-back mode, and enable wakeup event. Please refer to the datasheet ch.6.1 about setting the NCR register.

###4. clear TX status by reading the NSR register (REG_01).

The bit [2] TX1END, bit [3] TX2END, and bit [5] WAKEST will be automatically cleared by reading it or writing "1". Please refer to the datasheet ch.6.2 about the NSR register setting.

###5. Read the EEPROM saved data.

###6. Write Node address 6 bytes into the physical address registers (REG_10 ~ REG_15).

###7. Write Hash table 8 bytes into the multicast address registers (REG_16 ~ REG_1D).

###8. set the IMR register (REG_FF) PAR bit[7]=1 to enable the Pointer Automatic Return function, which is the memory read/ write address pointer of the RX/ TX FIFO SRAM.

###9. depend on OS and DDK of the system to handle the NIC interrupt or polling service.

###10. Program the IMR register (REG_FF) PRM bit [0]/ PTM bit [1] to enable the RX/ TX interrupt. Before doing this, the system designer needs to register the interrupt handler routine. For example, if the driver needs to generate the interrupt after one package is transmitted, the interrupt mask register IMR PTM bit [1] =1 will be set. And, if the interrupt is generated after the DM9000 received one new packet incoming, IMR PRM bit [0] should be set to "1".

###11. Program the RCR register to enable RX. The RX function is enabled by setting the RX control register (REG_05) RXEN bit [0] =1. The choice of the other bits bit [6:0] is depended on the system design. Please refer to the datasheet ch.6.6 about setting the RCR register.

###12. NIC is being activated and ready RX/ TX now.