Truly independent web browser

64kB intro for Revision 2023

Synthesizer plug-in (previously released as Vember Audio Surge)

An improved and personalized version of TJAPlayer3-Develop-Rewrite, .tja chart player axed on entertainment and creativity.

Chromium running inside your terminal

RISC-V out-of-order core for education and research purposes

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

IEC 62056 smart meter readout in perl

A modern hardware definition language and toolchain based on Python

A Python library for IEC62056-21, Local Data Readout of Energy Meters. Former IEC1107

Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference

Bluespec Compiler (BSC)

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

Effect handlers in C++

How to use the Intel JTAG primitive without using virtual JTAG

GitHub Action for continuous benchmarking to keep performance

An environmental monitoring and regulation system

Design document for RiscyOO processor

RiscyOO: RISC-V Out-of-Order Processor

RSD: RISC-V Out-of-Order Superscalar Processor

iCESugar series FPGA dev board

Build your hardware, easily!

Altera JTAG UART wrapper for Bluespec

Hardware Description Languages

A collection of reusable Clash designs/examples

Tomu FPGA (Fomu for short), a FPGA which fits inside your USB port!

Generate interface between Clash and Verilator

Converts Hikvision camera events to MQTT

Coding practice tool with automatic grading and LTI integration