Skip to content
View susululu's full-sized avatar
Block or Report

Block or report susululu

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Verilog code for a 16 point FFT for FPGA

Verilog 5 Updated Apr 26, 2020

A simple demo of an FFT project for the Nexys 4 FPGA

Verilog 7 10 Updated Oct 31, 2017

用Verilog语言编写,实现2FSK,2PSK, 2DPSK, QPSK调制解调

Verilog 31 21 Updated Mar 15, 2019

主要记录计算机视觉、VSLAM、点云、结构光、机械臂抓取、三维重建、深度学习、自动驾驶等前沿paper与文章。

526 82 Updated Jan 17, 2024

「3D视觉(三维重建、SLAM、AR/VR) + 传统图像处理 + 计算机视觉(偏AI) 」重要知识点和面试问题。

C++ 437 74 Updated Oct 24, 2020

Serializer/Deserializer .vhd files and report

VHDL 1 Updated Jan 19, 2017

Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS

Verilog 43 18 Updated Oct 20, 2022

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Verilog 47 12 Updated Nov 23, 2013
Verilog 2 Updated Jul 18, 2016

FFT implementation using CORDIC algorithm written in Verilog.

Verilog 23 8 Updated Sep 6, 2018

LMS-Adaptive Filter implement using verilog and Matlab

Verilog 34 12 Updated Oct 21, 2016

Ethernet 10GE MAC

Verilog 45 25 Updated Jul 17, 2014

Ethernet 100/1000 Mbps

VHDL 2 3 Updated Jul 17, 2014

基于 UDP 协议的千兆以太网视频外挂ddr3存储并hdmi显示和心率数据传输

Verilog 1 1 Updated Mar 16, 2022

FPGA,锆石的板子,rom实现win7式屏保(coding移过来),下回改成sdram或者ddr3试试

Verilog 3 Updated Sep 29, 2017

SPI通信实现FLASH读写

Verilog 12 3 Updated Mar 18, 2020

Greedy Gaussian Segmentation

Python 96 33 Updated Jan 2, 2023
Python 452 160 Updated Jun 14, 2020

An Online Algorithm for Segmenting Time Series

Python 5 2 Updated Mar 21, 2019

Verilog PCI express components

Verilog 1,035 275 Updated Apr 26, 2024

ARIMA, DBN,FFNN,GBRT,LSTM,RFR,SEQ2SEQ,SVR,XGBOOST

Python 22 4 Updated Mar 15, 2019

TensorFlow implementation of N-BEATS model for univariate time series forecasting.

Python 16 4 Updated Jun 17, 2024

通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器

Verilog 184 45 Updated Mar 2, 2022

和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS

77 13 Updated Nov 21, 2020

计算机视觉算法工程师实习生面试总结 (微软、阿里、商汤、海康、华为、平安offer)

394 61 Updated Sep 9, 2019

N-BEATS is a neural-network based model for univariate timeseries forecasting. N-BEATS is a ServiceNow Research project that was started at Element AI.

Python 497 114 Updated Aug 8, 2022

NBEATS implementation in Tensorflow 2.x

Jupyter Notebook 2 Updated Jan 19, 2022

An comprehensive summary on NBeats Re-implementation

Python 9 1 Updated Aug 20, 2020

线段树的实现

Python 1 Updated Apr 9, 2017

这是一个嵌入式物联网开源项目。以一个无线传感控制网络项目为实际案例,开源了一些无线控制模块和传感器模块。

93 42 Updated Jan 29, 2021
Next