Verilog-A Preisach ferroelectric cap (PFECAP) simulation model for FET

FET model should be modded to have charge output pin as it was done here: https://nanohub.org/publications/95/5

Coded by: Alexey Leushin

Advisors: Popov V.P., Tarkov M.S.

Novosibirsk, ISP, 2019

License: GPL2

Based on:

1. Bo Jiang et al. "Computationally Efficient Ferroelectric Capacitor Model for Circuit Simulation". Symposium on VLSl Technology Digest of Technical Papers, 141-142 (1997)
2. K. Ni et al. "A circuit compatible accurate compact model for ferroelectric FETs". IEEE Symposia on VLSI Technology & Circuits, 131–132 (2018)
3. K. Ni et al. "Critical Role of Interlayer in Hf[0.5]Zr[0.5]O[2] Ferroelectric FET Nonvolatile Memory Performance". IEEE Transactions On Electron Devices, Vol. 65, No. 6, 2461–2469 (2018)