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A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX

Verilog 2 Updated Aug 6, 2024

多周期CPU(MIPS指令集), 支持其中54条指令. (From 同济大学计算机组成原理课程设计)

Verilog 1 Updated Jul 24, 2024

Try to make sense of example FPGA Code for a PCIe card from Aliexpress

Verilog 1 Updated Jun 8, 2024

边缘设备端算法部署模板框架(包括海思SS928、Hi3519 DV500;瑞芯微rv1126、rk588、比特大陆BM1684X),部署项目包括yolov5、picodet、MNIST,包括优化加速教程

C++ 5 2 Updated Jul 17, 2024

Simulador de un sensor acustico distribuido basado en fibra óptica haciendo uso de la tecnica de reflectometria óptica en el dominio temporal

MATLAB 1 Updated Jul 14, 2024

【2023全国大学生FPGA 创新设计竞赛】全国二等奖作品:Cortex-M0智能飞机大战游戏机 开源项目

Verilog 12 Updated Jul 13, 2024

IMPLEMENTATION OF IMAGE SUPER RESOLUTION NETWORK BASED ON THE XILINX ZYNQ ULTRASCALE+ MPSOC - ZCU102 EVALUATION KIT

Python 1 Updated Jul 12, 2024

This repository contains the .ipynb files for implementing a hybrid deep learning model aimed at performing fault detection and diagnosis in cyber-physical systems

Jupyter Notebook 1 Updated Aug 30, 2024

PUF GO:基于物理不可克隆函数的集成可信安全系统 随着信息技术的快速发展和互联网的普及,用户和企业对于数据安全、隐私保护和系统可靠性的关注越来越高。物理不可克隆函数(PUF)作为一类新型硬件密码原语,具有免密钥、轻量级、防篡改等特点,能够作为可信执行环境的硬件安全基础。本项目在FPGA芯片上实现PUF电路,将PUF电路与LoongArch架构微处理器结合,通过PUF提供硬件可信根,从而在…

Verilog 2 Updated Jul 10, 2024

Tesi triennale in Fisica: "Sistema di comunicazione ottico basato su FPGA per l’esperimento CUPID"

VHDL 2 Updated Jul 14, 2024

This repo is Pytorch implementation of Masked AutoEncoder Pretraining (MAE) for Mechanical Fault Diagnosis.

Python 4 1 Updated Jul 7, 2024

Code for Research Article Deciphering the Optimal Radar Ensemble for Advancing Sleep Posture Prediction through a Multiview Convolutional Neural Network (MVCNN) Using Spatial Radio Echo Map (SREM)

Python 1 Updated Jul 4, 2024

Potential portfolio project for my time at DSR Berlin. Detecting sleep apnea from smartphone microphone recordings of sleep sounds.

Jupyter Notebook 2 Updated Sep 5, 2024

FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Verilog 27 6 Updated Jul 4, 2024

A rnn-cnn based network for sleep stage classification using ECG signals.

Python 2 1 Updated Aug 27, 2024

The frequency spectrum features were extracted from EEG by the power spectral density(PSD), and then the features were classified into emotions by Gated Recurrent Unit(GRU) with attention mechanis…

Python 2 Updated May 14, 2024

This on-chip system, designed for high efficiency and accuracy, is based on Very Large Scale Integration (VLSI) and employs a nonlinear Support Vector Machine (SVM). It comprises a feature extracti…

Verilog 4 Updated Oct 21, 2023

Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - 🇧🇩

Verilog 1 Updated Apr 7, 2024
Verilog 1 Updated Jun 30, 2023

An FPGA Implementation for ECG Classification Inference with Spiking Neural Network

Verilog 2 Updated Jun 24, 2024

Summer Internship Project @ IIT Roorkee 2024

Verilog 1 Updated Jun 28, 2024

Codes for the paper "MENTAL STRESS DETECTION FROM ULTRA-SHORT HEART RATE VARIABILITY USING EXPLAINABLE GRAPH CONVOLUTIONAL NETWORK WITH NETWORK PRUNING AND QUANTISATION"

Python 3 Updated Aug 3, 2023

Winter 2024 - Heart Rate Variability Processing with Artificial Intelligence Techniques.

Python 2 Updated Mar 21, 2024

Prediction of Cardiovascular Diseases with Heart Rate Variability Data and Machine Learning

Python 1 Updated Apr 23, 2024
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