Merge pull request #2394 from fpistm/STM32CubeF7_update

chore(f7): update to latest STM32CubeF7 v1.17.2
stm32duino · Jun 7, 2024 · 4fa3322 · 4fa3322
2 parents 483c954 + 111c046
commit 4fa3322
Show file tree

Hide file tree

Showing 166 changed files with 7,156 additions and 4,607 deletions.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h
@@ -6588,7 +6588,7 @@ typedef struct
 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
 #define FMC_BCR1_CCLKEN_Pos (20U)
 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
 #define FMC_BCR1_WFDIS_Pos (21U)
 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7491,7 +7491,7 @@ typedef struct
 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
 #define FMC_SDRTR_REIE_Pos (14U)
 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
 
 /****************** Bit definition for FMC_SDSR register ******************/
 #define FMC_SDSR_RE_Pos (0U)
@@ -11413,7 +11413,7 @@ typedef struct
 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
 
-/****************** Bit definition for SDMMC_STA registe ********************/
+/****************** Bit definition for SDMMC_STA register ********************/
 #define SDMMC_STA_CCRCFAIL_Pos (0U)
 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12750,7 +12750,7 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
 
-/******************* Bit definition for TIM_OR regiter *********************/
+/******************* Bit definition for TIM_OR register *********************/
 #define TIM_OR_TI4_RMP_Pos (6U)
 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13007,7 +13007,7 @@ typedef struct
 /* */
 /******************************************************************************/
 /*
- * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
  */
 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
 #define USART_TCBGT_SUPPORT

diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h
@@ -6604,7 +6604,7 @@ typedef struct
 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
 #define FMC_BCR1_CCLKEN_Pos (20U)
 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
 #define FMC_BCR1_WFDIS_Pos (21U)
 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7507,7 +7507,7 @@ typedef struct
 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
 #define FMC_SDRTR_REIE_Pos (14U)
 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
 
 /****************** Bit definition for FMC_SDSR register ******************/
 #define FMC_SDSR_RE_Pos (0U)
@@ -11435,7 +11435,7 @@ typedef struct
 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
 
-/****************** Bit definition for SDMMC_STA registe ********************/
+/****************** Bit definition for SDMMC_STA register ********************/
 #define SDMMC_STA_CCRCFAIL_Pos (0U)
 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12772,7 +12772,7 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
 
-/******************* Bit definition for TIM_OR regiter *********************/
+/******************* Bit definition for TIM_OR register *********************/
 #define TIM_OR_TI4_RMP_Pos (6U)
 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13029,7 +13029,7 @@ typedef struct
 /* */
 /******************************************************************************/
 /*
- * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
  */
 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
 #define USART_TCBGT_SUPPORT

diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h
@@ -6818,7 +6818,7 @@ typedef struct
 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
 #define FMC_BCR1_CCLKEN_Pos (20U)
 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
 #define FMC_BCR1_WFDIS_Pos (21U)
 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7721,7 +7721,7 @@ typedef struct
 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
 #define FMC_SDRTR_REIE_Pos (14U)
 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
 
 /****************** Bit definition for FMC_SDSR register ******************/
 #define FMC_SDSR_RE_Pos (0U)
@@ -11658,7 +11658,7 @@ typedef struct
 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
 
-/****************** Bit definition for SDMMC_STA registe ********************/
+/****************** Bit definition for SDMMC_STA register ********************/
 #define SDMMC_STA_CCRCFAIL_Pos (0U)
 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12995,7 +12995,7 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
 
-/******************* Bit definition for TIM_OR regiter *********************/
+/******************* Bit definition for TIM_OR register *********************/
 #define TIM_OR_TI4_RMP_Pos (6U)
 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13252,7 +13252,7 @@ typedef struct
 /* */
 /******************************************************************************/
 /*
- * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
  */
 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
 #define USART_TCBGT_SUPPORT

diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h
@@ -6802,7 +6802,7 @@ typedef struct
 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
 #define FMC_BCR1_CCLKEN_Pos (20U)
 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
 #define FMC_BCR1_WFDIS_Pos (21U)
 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7705,7 +7705,7 @@ typedef struct
 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
 #define FMC_SDRTR_REIE_Pos (14U)
 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
 
 /****************** Bit definition for FMC_SDSR register ******************/
 #define FMC_SDSR_RE_Pos (0U)
@@ -11636,7 +11636,7 @@ typedef struct
 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
 
-/****************** Bit definition for SDMMC_STA registe ********************/
+/****************** Bit definition for SDMMC_STA register ********************/
 #define SDMMC_STA_CCRCFAIL_Pos (0U)
 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12973,7 +12973,7 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
 
-/******************* Bit definition for TIM_OR regiter *********************/
+/******************* Bit definition for TIM_OR register *********************/
 #define TIM_OR_TI4_RMP_Pos (6U)
 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13230,7 +13230,7 @@ typedef struct
 /* */
 /******************************************************************************/
 /*
- * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
  */
 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
 #define USART_TCBGT_SUPPORT

diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h
@@ -6818,7 +6818,7 @@ typedef struct
 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
 #define FMC_BCR1_CCLKEN_Pos (20U)
 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
 #define FMC_BCR1_WFDIS_Pos (21U)
 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7721,7 +7721,7 @@ typedef struct
 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
 #define FMC_SDRTR_REIE_Pos (14U)
 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
 
 /****************** Bit definition for FMC_SDSR register ******************/
 #define FMC_SDSR_RE_Pos (0U)
@@ -11658,7 +11658,7 @@ typedef struct
 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
 
-/****************** Bit definition for SDMMC_STA registe ********************/
+/****************** Bit definition for SDMMC_STA register ********************/
 #define SDMMC_STA_CCRCFAIL_Pos (0U)
 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12995,7 +12995,7 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
 
-/******************* Bit definition for TIM_OR regiter *********************/
+/******************* Bit definition for TIM_OR register *********************/
 #define TIM_OR_TI4_RMP_Pos (6U)
 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13252,7 +13252,7 @@ typedef struct
 /* */
 /******************************************************************************/
 /*
- * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
  */
 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
 #define USART_TCBGT_SUPPORT