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probe-run -> probe-rs #369

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Oct 29, 2023
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2 changes: 1 addition & 1 deletion .cargo/config.toml
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
runner = "probe-run --chip STM32WLE5JCIx --connect-under-reset"
runner = "probe-rs run --chip STM32WLE5JCIx --connect-under-reset"
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "link-arg=-Tdefmt.x",
Expand Down
4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -118,8 +118,8 @@ jobs:
timeout-minutes: 5
run: |
python3 testsuite/runall.py --elf-dir bins \
002900205553500A20393256 \
0034001A5553500B20393256
0483:374e:002900205553500A20393256 \
0483:374e:0034001A5553500B20393256

test:
name: Unit Tests
Expand Down
9 changes: 4 additions & 5 deletions testsuite/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,7 @@ These tests will run automatically as part of CI for every pull-request.
## Quickstart

* `rustup target add --toolchain stable thumbv7em-none-eabi` ([rustup])
* `cargo install probe-run` ([probe-run])
* ⚠️ You must use version >=0.3.1 to avoid bugs with the STM32WL ⚠️
* `cargo install probe-rs --features cli` ([probe-rs])
* Linux users: Add udev rules

```text
Expand All @@ -28,7 +27,7 @@ SUBSYSTEM=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", MODE="0666"
```console
$ DEFMT_LOG=info cargo test -p testsuite --target thumbv7em-none-eabi --bin pka
Finished dev [optimized + debuginfo] target(s) in 0.01s
Running `probe-run --chip STM32WLE5JCIx --connect-under-reset target/thumbv7em-none-eabi/debug/pka`
Running `probe-rs run --chip STM32WLE5JCIx --connect-under-reset target/thumbv7em-none-eabi/debug/pka`
(HOST) INFO flashing program (17.31 KiB)
(HOST) INFO success!
────────────────────────────────────────────────────────────────────────────────
Expand Down Expand Up @@ -68,7 +67,7 @@ Assuming both boards are connected to the same system you will have to pass a
specific probe to each.

```console
$ probe-run --list-probes
$ probe-rs list
The following devices were found:
[0]: STLink V3 (VID: 0483, PID: 374e, Serial: 001D00145553500A20393256, STLink)
[1]: STLink V3 (VID: 0483, PID: 374e, Serial: 001600345553500A20393256, STLink)
Expand All @@ -77,5 +76,5 @@ $ DEFMT_LOG=info cargo test -p testsuite --target thumbv7em-none-eabi --bin subg
```

[defmt-test]: https://crates.io/crates/defmt-test
[probe-run]: https://github.com/knurling-rs/probe-run
[probe-rs]: https://github.com/probe-rs/probe-rs
[rustup]: https://rustup.rs/
3 changes: 2 additions & 1 deletion testsuite/runall.py
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,8 @@ async def probe_run(elf_path: str, probe: str, log_prefix: str) -> TestResult:
print(f"[{log_prefix}] Running {elf_path}")
start = time.monotonic()
proc = await asyncio.create_subprocess_exec(
"probe-run",
"probe-rs",
"run",
"--chip",
"STM32WLE5JCIx",
"--connect-under-reset",
Expand Down
4 changes: 2 additions & 2 deletions testsuite/src/rcc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ impl SysClkSrc {

const LPRUN_RANGES: [LprunRange; 4] = [
// STLink drops the connection when switching to 100k
// with the default JTAG clock frequency set by probe-run
// with the default JTAG clock frequency set by probe-rs
// LprunRange::Range100k,
LprunRange::Range200k,
LprunRange::Range400k,
Expand All @@ -63,7 +63,7 @@ const CLKS: [SysClkSrc; 14] = [
SysClkSrc::Hse(Vos::V1_0),
SysClkSrc::Hse(Vos::V1_2),
// STLink drops the connection when switching to 100k
// with the default JTAG clock frequency set by probe-run
// with the default JTAG clock frequency set by probe-rs
// SysClkSrc::Msi(MsiRange::Range100k),
SysClkSrc::Msi(MsiRange::Range200k),
SysClkSrc::Msi(MsiRange::Range400k),
Expand Down