HLS & hls4ml Tutorial

32-bit RISC-V CPU in ~800 lines of C89

Docker installation of Vivado tooling

Tutorial notebooks for hls4ml

Machine learning on FPGAs using HLS

AI High-Performance Solution on FPGA

This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.

Hands-on experience using Vivado with Xilinx FPGA hardware

A 16-Bit computer(C.I.S.C) with 38 Instructions, 2 addressing modes and a register stack.

Pynq computer vision examples with an OV5640 camera

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

AMD University Program HLS tutorial

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Project F brings FPGAs to life with exciting open-source designs you can build on.

A Tutorial on Putting High-Level Synthesis cores in PYNQ

PYNQ Bootcamp 2019-2024 teaching materials.

RISC-V Integration for PYNQ

Learning FPGA, yosys, nextpnr, and RISC-V

A Linux-capable RISC-V multicore for and by the world

VRoom! RISC-V CPU

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

📚 Learn to write an embedded OS in Rust 🦀

Open-source high-performance RISC-V processor

Linux source code for ISCA 2020 paper "Enhancing and Exploiting Contiguity for Fast Memory Virtualization"

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Marginally better than redstone

RSD: RISC-V Out-of-Order Superscalar Processor