sober31

sober31

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6 stars written in Verilog

uvm AXI BFM(bus functional model)

Verilog 233 113 Updated Jun 23, 2013

This is the main repository for all the examples for the book Practical UVM

Verilog 172 108 Updated Oct 21, 2020

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

Verilog 93 33 Updated Jan 17, 2018

PCIE 5.0 Graduation project (Verification Team)

Verilog 55 23 Updated Jan 27, 2024

my UVM training projects

Verilog 28 11 Updated Mar 14, 2019

This is the main repository for all the examples for the book Practical UVM

Verilog 1 Updated Oct 21, 2020