CGRA Compilation Framework

armchina NPU driver

Verilog AXI components for FPGA implementation

Code for the paper: Fully Trainable and Interpretable Non-Local Sparse Models for Image Restoration (ECCV 2020)

Official implementation for "DRL-ISP: Multi-Objective Camera ISP with Deep Reinforcement Learning"

This repository explains use of a full system simulator to simulate benchmarks in a multinode environment

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

SystemC/TLM-2.0 Co-simulation framework

Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

FinGAT: A Financial Graph Attention Networkto Recommend Top-K Profitable Stocks

The GitHub repository for the paper "Informer" accepted by AAAI 2021.