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i8080 precise replica in Verilog, based on reverse engineering of real die

Verilog 151 21 Updated Jul 13, 2019

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Verilog 317 63 Updated Jul 12, 2017

RSD: RISC-V Out-of-Order Superscalar Processor

SystemVerilog 981 98 Updated Sep 4, 2024

A tiny Open POWER ISA softcore written in VHDL 2008

Verilog 655 99 Updated Aug 17, 2024

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation…

Verilog 42 7 Updated May 9, 2024

Exploring gate level simulation

Verilog 55 4 Updated Sep 18, 2022

32-bit Superscalar RISC-V CPU

Verilog 850 146 Updated Sep 18, 2021

Paranoid's library contains implementations of checks for well known weaknesses on cryptographic artifacts.

Python 785 47 Updated Apr 12, 2024

Unsigned code loader for Amlogic BootROM

C 68 24 Updated Nov 6, 2022

kCTF is a Kubernetes-based infrastructure for CTF competitions. For documentation, see

Go 659 73 Updated Sep 15, 2024

End-To-End is a crypto library to encrypt, decrypt, digital sign, and verify signed messages (implementing OpenPGP)

JavaScript 4,128 298 Updated Apr 9, 2023

E2EMail is a simple Chrome application - a Gmail client that exchanges OpenPGP mail.

JavaScript 806 62 Updated Feb 28, 2017

Counterparty web wallet

JavaScript 147 163 Updated Mar 29, 2024

OpenCheck es una plataforma web y móvil para conectar establecimientos (restaurants/bars y retail stores) con clientes on-the-go.

Python 5 Updated Aug 14, 2010

The new version of aMSN client

Python 1 1 Updated Dec 12, 2009

The new version of aMSN client

Python 108 149 Updated Nov 24, 2009