Skip to content
View sevjaeg's full-sized avatar
  • Vienna

Block or report sevjaeg

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. hwpe-aes hwpe-aes Public

    Project for 384.178 SoC Design Lab (2021W) and 384.180 SoC Advanced (2022S)

    Verilog

  2. a-little-riscy a-little-riscy Public

    Project for 191.105 Advanced Computer Architecture (2020W)

    Scala

  3. fault-tolerant-computing fault-tolerant-computing Public

    Seminar Thesis for 376.073 System Architectures for Automation and Control (2020W)

    TeX

  4. near-thresholds-srams near-thresholds-srams Public

    Seminar Thesis for 354.072 Seminar Mixed-Signal ICs (2021S)

    TeX

  5. picorv32 picorv32 Public

    Forked from YosysHQ/picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog 1 1

  6. wait-free-ll wait-free-ll Public

    Project for 184.726 Advanced Multiprocessor Programming (2020S)

    C++ 1