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  1. VSD_PLL VSD_PLL Public

    Phase-Locked-Loop (PLL) -Design-using-SKY130nm-Technology

  2. Phase-Locked-Loop-Design-using-SKY130nm-Technology Phase-Locked-Loop-Design-using-SKY130nm-Technology Public

    Forked from MarichamyDivya/Phase-Locked-Loop-Design-using-SKY130nm-Technology

    Workshop, 31 July 2021 and 1 August 2021

  3. Phase-Locked-Loop Phase-Locked-Loop Public

    Forked from abdullahmohamed2540/Phase-Locked-Loop

    Design PLL in 130nm

  4. VSD_Workshop VSD_Workshop Public

    Phase_Locked Loop IC Design

  5. Elevator Elevator Public

    Capture the bug hackathon

    Verilog

  6. Enabling-Binary-Neural-Network-Training-on-the-Edge Enabling-Binary-Neural-Network-Training-on-the-Edge Public

    Forked from awai54st/Enabling-Binary-Neural-Network-Training-on-the-Edge

    C++