Shichao's Notes

Python interface to PCIE

An interactive playground for Scala

Visual Leak Detector for Visual C++ 2008-2015

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

Recipe for FPGA cooking

SLAC Python Based Hardware Abstraction & Data Acquisition System

A huge VHDL library for FPGA development

Python Display Manager

A Just-In-Time Compiler for Verilog from VMware Research

Xilinx Virtual Cable Daemon

XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.

Xilinx Virtual Cable server for FT2232H (targeted for ARM SBCs)

ESP8266 Xilinx Virtual Cable - wifi JTAG

public domain tools for FPGAs

USB SMBus Interface

Programs a Spartan 6 FPGA over JTAG using an FTDI USB chip.

Simple command line utility for converting .doc & .xls files to any supported format such as Text, RTF, CSV or PDF

Verilog AXI components for FPGA implementation

Reference HDL code for the MATRIX Creator's Spartan 6 FPGA

Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1

Driver and libraries for FPGA PCIe firmware used by PERG team and available on OHWR.

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

IP-core package generator for AXI4/Avalon

VUnit is a unit testing framework for VHDL/SystemVerilog

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Linux kernel variant from Analog Devices; see README.md for details