Verilog PCI express components

Verilog Ethernet components for FPGA implementation

PCI express simulation framework for Cocotb

Open source FPGA-based NIC and platform for in-network compute

A cli tool to browse and play anime

mmm lobster

🛠Helpful items for making open source hardware projects.

RTL, Cmodel, and testbench for NVDLA

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

HDMI Out VHDL code for 7-series Xilinx FPGAs

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

VHDL course at Brno University of Technology

PhyWhisperer-USB: Hardware USB Trigger

Simple UART controller for FPGA written in VHDL

SNES for the Analogue Pocket

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

Space Invaders game implemented with VHDL

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

VUnit is a unit testing framework for VHDL/SystemVerilog

Haskell to VHDL/Verilog/SystemVerilog compiler

A FPGA friendly 32 bit RISC-V CPU implementation

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.