3-stage RV32IMACZb* processor with debug

RSD: RISC-V Out-of-Order Superscalar Processor

Machine learning on FPGAs using HLS

Clash的桌面客户端，支持 windows、linux、macos

Gigabit MAC + UDP/TCP/IP offload Engine

This repo contains the Limago code

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

A Fast, Low-Overhead On-chip Network

A Linux-capable RISC-V multicore for and by the world

This repository consists of RTL, constraints and reports for the paper accepted in Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Shanghai, P.R. China, December 16-18, 2021.

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

A tool which is uses to remove Windows Defender in Windows 8.x, Windows 10 (every version) and Windows 11.

Collection of tutorials from the BYU Computer Engineering Group

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

The Ultra-Low Power RISC-V Core

🌊 Digital timing diagram rendering engine

Tengine is a lite, high performance, modular inference engine for embedded device

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Open source FPGA-based NIC and platform for in-network compute

SonicBOOM: The Berkeley Out-of-Order Machine

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

A comprehensive mapping database of English to Chinese technical vocabulary in the artificial intelligence domain

achieve softmax in PYNQ with heterogeneous computing.

PicoRV32 - A Size-Optimized RISC-V CPU

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Basic floating-point components for RISC-V processors

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

Implement Tiny YOLO v3 on ZYNQ

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.