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scr1
scr1 PublicForked from syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog 1
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VerilogCodeECC
VerilogCodeECC PublicForked from raya4213/VerilogCodeECC
Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field
Jupyter Notebook
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Verilog-Design-Examples
Verilog-Design-Examples PublicForked from snbk001/Verilog-Design-Examples
tbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bi…
Verilog
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core_usb_cdc
core_usb_cdc PublicForked from ultraembedded/core_usb_cdc
Basic USB-CDC device core (Verilog)
Verilog
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