Increase riscv implementation in DepthwiseConvKernel

[zhangfeiv0]

Summary:

Increase riscv implementation in DepthwiseConvKernel.

Compile:

export USE_CUDA=0
export USE_DISTRIBUTED=0
export USE_MKLDNN=0
export MAX_JOBS=4
export CMAKE_CXX_COMPILER=clang++
export CMAKE_C_COMPILER=clang
export CMAKE_C_FLAGS=-march=rv64gcv
export CMAKE_CXX_FLAGS=-march=rv64gcv
python3 setup.py develop --cmake

Test Plan:

Correctness - Check the results of the run before and after test_convolution.py

python3 test/run_test.py --include nn/test_convolution --keep-going

Before:
===== 9 passed, 13 skipped, 564 deselected in 46.55s =====
The following tests failed consistently:
test/nn/test_convolution.py::TestConvolutionNN::test_Conv2d_backward_twice
test/nn/test_convolution.py::TestConvolutionNN::test_Conv2d_inconsistent_types
test/nn/test_convolution.py::TestConvolutionNN::test_conv_modules_raise_error_on_incorrect_input_size
test/nn/test_convolution.py::TestConvolutionNN::test_conv_shapecheck
test/nn/test_convolution.py::TestConvolutionNN::test_invalid_conv1d
test/nn/test_convolution.py::TestConvolutionNN::test_invalid_conv2d
test/nn/test_convolution.py::TestConvolutionNN::test_invalid_conv3d
test/nn/test_convolution.py::TestConvolutionNN::test_mismatch_shape_conv2d
test/nn/test_convolution.py::TestConvolutionNNDeviceTypeCPU::test_conv_empty_channel_cpu_complex64
test/nn/test_convolution.py::TestConvolutionNNDeviceTypeCPU::test_conv_empty_channel_cpu_float32

After:
===== 9 passed, 13 skipped, 564 deselected in 48.13s =====
The following tests failed consistently:
test/nn/test_convolution.py::TestConvolutionNN::test_Conv2d_backward_twice
test/nn/test_convolution.py::TestConvolutionNN::test_Conv2d_inconsistent_types
test/nn/test_convolution.py::TestConvolutionNN::test_conv_modules_raise_error_on_incorrect_input_size
test/nn/test_convolution.py::TestConvolutionNN::test_conv_shapecheck
test/nn/test_convolution.py::TestConvolutionNN::test_invalid_conv1d
test/nn/test_convolution.py::TestConvolutionNN::test_invalid_conv2d
test/nn/test_convolution.py::TestConvolutionNN::test_invalid_conv3d
test/nn/test_convolution.py::TestConvolutionNN::test_mismatch_shape_conv2d
test/nn/test_convolution.py::TestConvolutionNNDeviceTypeCPU::test_conv_empty_channel_cpu_complex64
test/nn/test_convolution.py::TestConvolutionNNDeviceTypeCPU::test_conv_empty_channel_cpu_float32

Performance - Compare the results before and after mobilenet_v2

python3 run.py mobilenet_v2 -d cpu -t eval

Before:
Running eval method from mobilenet_v2 on cpu in eager mode with input batch size 16 and precision fp32.
CPU Wall Time per batch: 19590.647 milliseconds
CPU Wall Time: 19590.647 milliseconds
Time to first batch: 5271.3518 ms
CPU Peak Memory: 0.3809 GB

After:
Running eval method from mobilenet_v2 on cpu in eager mode with input batch size 16 and precision fp32.
CPU Wall Time per batch: 13523.530 milliseconds
CPU Wall Time: 13523.530 milliseconds
Time to first batch: 2696.0304 ms
CPU Peak Memory: 0.3408 GB

Versions:
Clang version: 17.0.2
Platform: CanMV-K230
Architecture: riscv64
OS: Ubuntu 23.10

cc @jgong5 @mingfeima @XiaobingSuper @sanchitintel @ashokei @jingxu10

[linux-foundation-easycla]

The committers listed above are authorized under a signed CLA.

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✅ You can merge normally! (1 Unrelated Failure)

As of commit 10f8b73 with merge base 7ef7c26 ():

UNSTABLE - The following job failed but was likely due to flakiness present on trunk and has been marked as unstable:

• pull / linux-focal-cuda12.4-py3.10-gcc9-sm86 / test (default, 5, 5, linux.g5.4xlarge.nvidia.gpu, unstable) (gh)
  FAILED

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[wangfanv0]

This is our attempt at implementing RVV. Based on the code implementation, it does not negatively impact the original PyTorch build. Additionally, we observed significant performance improvements when performing inference on MobileNet_v2. With input data of [1, 3, 224, 224], we saw a 3x performance increase.
Has anyone followed up on this PR?
@mikaylagawarecki @ezyang

[ezyang]

This would be the very first riscv kernel we'd add to PyTorch. I'm not sure if we want to commit to maintaining all of these kernels. @malfet for more comments.

[zhangfeiv0]

@malfet do you have any suggestions？

[zhangfeiv0]

@malfet @ezyang We are committed to continuously optimizing and maintaining the performance of PyTorch on the RISC-V architecture. We hope to have someone review our code.

[ezyang]

cc @albanD

[malfet]

This code is not nested by CI, but sure, why not (considering that NEON code is there)
But one should probably start with vec sublibary if they are serious about RISC-V performance

[malfet]

@pytorchbot merge -f "Lint is green, the rest is not compiled"

[pytorchmergebot]

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