[synth] Increase FPU latency.

pulp-platform · Nov 6, 2021 · 6776687 · 6776687
1 parent 4c9a3ad
commit 6776687
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Showing 2 changed files with 9 additions and 8 deletions.
diff --git a/rtl/include/riscv_defines.sv b/rtl/include/riscv_defines.sv
@@ -394,14 +394,14 @@ parameter C_FPNEW_FMTBITS = fpnew_pkg::FP_FORMAT_BITS;
 parameter C_FPNEW_IFMTBITS = fpnew_pkg::INT_FORMAT_BITS;
 
 // Latency of FP operations: 0 = no pipe registers, 1 = 1 pipe register etc.
-parameter int unsigned C_LAT_FP64 = 'd0;
-parameter int unsigned C_LAT_FP32 = 'd0;
-parameter int unsigned C_LAT_FP16 = 'd0;
-parameter int unsigned C_LAT_FP16ALT = 'd0;
-parameter int unsigned C_LAT_FP8 = 'd0;
-parameter int unsigned C_LAT_DIVSQRT = 'd1; // divsqrt post-processing pipe
-parameter int unsigned C_LAT_CONV = 'd0;
-parameter int unsigned C_LAT_NONCOMP = 'd0;
+parameter int unsigned C_LAT_FP64 = 'd1;
+parameter int unsigned C_LAT_FP32 = 'd1;
+parameter int unsigned C_LAT_FP16 = 'd1;
+parameter int unsigned C_LAT_FP16ALT = 'd1;
+parameter int unsigned C_LAT_FP8 = 'd1;
+parameter int unsigned C_LAT_DIVSQRT = 'd2; // divsqrt post-processing pipe
+parameter int unsigned C_LAT_CONV = 'd1;
+parameter int unsigned C_LAT_NONCOMP = 'd1;
 
 // General FPU-specific defines
 

diff --git a/rtl/riscv_core.sv b/rtl/riscv_core.sv
@@ -28,6 +28,7 @@
 // and the FPU //
 // //
 ////////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
 
 import apu_core_package::*;