SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course

A scalable High-Level Synthesis framework on MLIR

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

Async-SDM-NoC

Verilog implementation of Mersenne Twister PRNG

通用VIP

Advanced Interface Bus (AIB) die-to-die hardware open source

Proxy: Next Generation Polymorphism in C++

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

RTL code of some arbitration algorithm

Verilog Ethernet Switch (layer 2)

10Gb Ethernet Switch

Switch ML Application

system paper reading notes

Simple, minimal implementation of the Mamba SSM in one file of PyTorch.

High-speed Large Language Model Serving on PCs with Consumer-grade GPUs

Installs Vivado on M1/M2/M3 macs

Image Processing Toolbox in Verilog using Basys3 FPGA

IP operations in verilog (simulation and implementation on ice40)

Image Signal Processor

xkISP：Xinkai ISP IP Core (HLS)

A simple and light-weight camera image processing pipeline

Image processing pipeline for cameras that provide raw data