waifu2x converter ncnn version, runs fast on intel / amd / nvidia / apple-silicon GPU with vulkan

Python Script to download hundreds of images from 'Google Images'. It is a ready-to-run code!

Verilog formatter

Simple 8-bit UART realization on Verilog HDL.

The final version of my custom 32-bit RISC CPU

An LLVM backend for my custom 32-bit RISC CPU https://scholarworks.rit.edu/theses/9550/

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

(LGPL) Demonstration of how to use a memory-mapped SDRAM through the Flexible Memory Controller

Audio pass-through STM32F769I-Discovery Line in buffer copied to Line out

Example OpenRISC backend

Project moved to: https://github.com/llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

Compiler from C to brainfuck

Verilog implementation of pipelined MIPS processor

MIPS CPU implemented in Verilog

MIPS single cycle Verilog implementation based on Computer Organization and Design by David A. Patterson and John L. Hennessy

The single instruction C compiler

Bits and Things - A dumping ground

Parameterized Booth Multiplier in Verilog 2001

Implementation of different types of adder circuits

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

VHDL codes of some binary adders.

Verilog Implementation of an ARM LEGv8 CPU

Kogge-Stone Adder in Verilog

Parallel Array of Simple Cores. Multicore processor.