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    66 repositories

    • website

      Public
      Public facing website
      Svelte
      •0•0•0•0•Updated Sep 21, 2024Sep 21, 2024

    • liteiclink

      Public
      Small footprint and configurable Inter-Chip communication cores
      Python
      •
      Other
      •25•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • liteeth

      Public
      Small footprint and configurable Ethernet core
      Python
      •
      Other
      •86•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • verilog-axis

      Public
      Verilog AXI stream components for FPGA implementation
      Python
      •
      MIT License
      •222•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • hls4ml

      Public
      Machine learning on FPGAs using HLS
      C++
      •
      Apache License 2.0
      •402•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • verible

      Public
      Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
      C++
      •
      Other
      •203•1•0•0•Updated Aug 12, 2024Aug 12, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •140•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •591•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • prjxray

      Public
      Documenting the Xilinx 7-series bit-stream format.
      Python
      •
      ISC License
      •149•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • RapidWright

      Public
      Build Customized FPGA Implementations for Vivado
      Java
      •
      Other
      •108•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •872•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • UHDM

      Public
      Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •40•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • cocotb

      Public
      cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •505•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • amaranth-soc

      Public
      System on Chip toolkit for Amaranth HDL
      Python
      •
      BSD 2-Clause "Simplified" License
      •30•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • amaranth

      Public
      A modern hardware definition language and toolchain based on Python
      Python
      •
      BSD 2-Clause "Simplified" License
      •170•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • openFPGALoader

      Public
      Universal utility for programming FPGA
      C++
      •
      Apache License 2.0
      •252•1•0•0•Updated Aug 12, 2024Aug 12, 2024

    • amaranth-boards

      Public
      Board definitions for Amaranth HDL
      Python
      •
      BSD 2-Clause "Simplified" License
      •109•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • litex-boards

      Public
      LiteX boards files
      Python
      •
      BSD 2-Clause "Simplified" License
      •279•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • litepcie

      Public
      Small footprint and configurable PCIe core
      Python
      •
      Other
      •116•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • litedram

      Public
      Small footprint and configurable DRAM core
      Python
      •
      Other
      •120•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • litespi

      Public
      Small footprint and configurable SPI core
      Python
      •
      BSD 2-Clause "Simplified" License
      •23•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • synlig

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •21•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • basejump_stl

      Public
      BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      •
      Other
      •97•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • litescope

      Public
      Small footprint and configurable embedded FPGA logic analyzer
      Python
      •
      Other
      •40•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • systemverilog-plugin

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •21•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • finn

      Public
      Dataflow compiler for QNN inference on FPGAs
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •230•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • finn-examples

      Public
      Dataflow QNN inference accelerator examples on FPGAs
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •57•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • esp

      Public
      Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
      C
      •
      Other
      •106•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • migen

      Public
      A Python toolbox for building complex digital hardware
      Python
      •
      Other
      •209•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • Surelog

      Public
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •68•0•0•0•Updated Aug 12, 2024Aug 12, 2024