Tags: openvizsla/ov_ftdi
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Osmocom requested changes, second batch (#48) * Fix rotated labels in schematic Some schmatic properties were rotated, making it difficult to read them in the PDF. * Search for all rotated text using the query: ((ObjectKind = 'Parameter') or (ObjectKind = 'Comment') or (ObjectKind = 'Designator') or (ObjectKind = 'Net Label')) And (Orientation <> '0 Degrees') * Manually rotate and re-position. * Reduce soldermask opening around U3 pins Addresses: https://osmocom.org/issues/5109 * Remove blanket soldermask opening under pins * Increase scope of previous soldermask design rule to include U3 * Allow un-powered operation Addresses: https://osmocom.org/issues/5063 * Introduce BAT60A diode between Vusb (from J1) and F1 * Introduce an alternative current path (also via BAT60A) between targetVBUS (from J2) and F1 * Place new components near J1, running the voltage trace on the inner power layer * Move C16 closwer to U9 * Update board revision to 3.4 As requested here: https://osmocom.org/issues/5160 * To reflect the change allowing the board to work unpowered * Improvements to TARGETVBUS and VUSB traces As requested in: https://osmocom.org/issues/5063 * Move TARGETVBUS vias away from J1 * Remove excess trace copper under C46 * Round corners of pads in D1 and D2 As requested in: https://osmocom.org/issues/5063#note-15 * Round pads, using the strategy from: https://osmocom.org/issues/5078#note-1
Osmocom updates for v3.3 production run (#46) * Move VBUS away from ground pad * Fixes: https://osmocom.org/issues/5070 * Resize 3.3V polygon under U9, and redraw VBUS trace * Resize edge-launch SMA pads Addresses issue: https://osmocom.org/issues/5069 * Reference pad size is: 1.75x3.125 * Pads on design were 1x3.8, resized to 1.75x3.8 (keeping same length, but making wider). * 25% round corner added as well, to match reference design * different connection between USB shield and GND Addresses issue https://osmocom.org/issues/5071 * Change shield-to-gorund topology of all USB connectors (J1, J2, J3) to a resistor/capacitor parallel connection * Increase size of shield-to-ground filter caps C44 and C48 from 0402 to 0603 * Required bookkeeping: extract all schematic and layout models to an internal library, so that the resistor and capacitor component models could be re-used * Note that only one side of each shield is connected to the ground-to-shield filter * Fix silkscreen font Addresses issue: https://osmocom.org/issues/5068 * Added DRC rule: Manufacturing->silk to soldermask clearance = 4mil * Increased text height to a minimum of 1mm * Labels re-arranged to fit, with minor via position adjustments to make space for the larger labels. * Fix single via restring violation Addresses https://osmocom.org/issues/5073 * Move via over. * Increase pad size on P1,P2,P3,P4 Fix for: https://osmocom.org/issues/5074 * Increase pad size of each pin (on all layers) from 1.5mm (.3mm annumlar ring width) to 1.9mm (.5mm annulacr ring width) in thru-hole headers P1,P2,P3,P4 * Minor adjustment of nearby tracks and silkscreen text to make room for larger pads * Increase test pad size from 30mil to 60mil Addresses https://osmocom.org/issues/5067 * Create new 60mil testpad footprint * Update test pads 1,2,3,4,13,14,15,16,17 with 60mil pad. Remaning test points are already large ground pads * Small adjustments to traces, vias, and silkscreen designators to make space for larger test pads * Increase spacing between thru-hole pads and power traces Addresses: https://osmocom.org/issues/5074#note-4 * J2,p4 to TARGETVBUS * J3,p1 to TARGETVBUS * J3,p5 to TARGETDTAP_P * P4,p26 to +5V * Un-tent all vias, and normalize via geometry Addresses: https://osmocom.org/issues/5064 * update all vias to have .3mm drill / .6mm pad size -> .15mm restring * Created a new DRC rule to enforce the .3mm/.6mm via geometry * set all vias to be untented * Created a new DRC rule to enforce a 0mm soldermask expansion on vias (so that the soldermask lines up directly with the outside of the via pad/restring area) * Small adjustments to silkscreen and via positions to enforce silk-to-soldermask clearance rule. * Round all SMD pads implement: https://osmocom.org/issues/5078 * Change all rectangular pads to rounded rect pads with a 30% corner radius * Geometry of pads that were already round are not modified. Note: This was done directly on the PCB, rather than replacing individual component footprints. If components are added/modified in the future, this may need to be reapplied. To select the rectangular pads, the following PCB filter was used: (ObjectKind = 'Pad') And (PadShape_AllLayers = 'Rectangular') Similarly, to select these pads (for further edits), a similar filter can be used: (ObjectKind = 'Pad') And (PadShape_AllLayers = 'Rounded Rectangle') And (Pad_CornerRadius_AllLayers = '30%') * Increase thermals on large SMD pads Addresses: https://osmocom.org/issues/5066 * Increase 'conductor width' of thermals between J4,J5, and TP5-TP12, from .254mm to .508mm * Remove potentially misleading component values Addresses: https://osmocom.org/issues/5075 * Remove component values from silkscreen * Remove pin # labels and tick marks from silkscreen * Verify that component designators are located next to the correct parts * Fix 1v2 and 5v labels on P4 * Correct typeface usage on thru-hole headers Addresses a further issue from: https://osmocom.org/issues/5075 * Change pin numbers on P1, P2, P3 to use 'calibri' font and same configuration (2mm height, bold) as rest of board. * Search for other text with incorrect typeface * Remove extraneous 'pcb edge' label on M1 layer * Add board fiducials Addresses: https://osmocom.org/issues/5086 -Create library component for fiducial -Add to the corners of the board * Remove solder paste openings from non-soldered pads Addresses: https://osmocom.org/issues/5086 - Modify 'ground pad', 'fiducial_1mm', 'testpoint-60mil', and 'EMPCB.SMAFSTJ.C.HT' library components to have no solder paste. - Update PCB with these components * Add P-CAD exports for the schematic and PCB design Addresses: https://osmocom.org/issues/5095 * PCAD schematic and PCB outputs added to Output Job * actual outputs checked in as well * Fix for commit 0760549 : P-CAD files added * Fix Pin label on P3 pin 19 Addresses: https://osmocom.org/issues/5075 * Incorrectly labeled as 'TDI'; changed to 'TDO' * Output job fix: Generate a DXF with the correct extension Addresses: https://osmocom.org/issues/5098 * Output generator had a bad configuration state, and was outputting a DXF while configured to output a DWG. Reset the configuration to produce a DXF with the proper extension. * AIncrease version number to v3.3 Addresses: https://osmocom.org/issues/5076 * Increase board minor version by 1 * Re-route differential traces to match PCB stackup Addresses: https://osmocom.org/issues/5108 Schematic: * Remove 'USB' net class * Add 'USB' differential pair class, and add 3 USB sets to it PCB: * Update layer stack with new board measurements (as a reference only; this doesn't directly affect the design) * Remove single-ended width rule for USB net class * Add differential pairs routing rule for 'USB' differential pair class * Add length matching rule for 'USB' differential pair class * Re-route each differential pair, taking care to match lengths by adding meanders during the routing. * Reduce solder stop opening sizes for pads of U2, U4 and U7 Addresses: https://osmocom.org/issues/5109 * Check that minimum solder mask sliver rule exists, and is enabled in DRC * Add new 'Solder mask expansion' rule, with an expansion of .03mm, matching pads in U2, U4 and U7. * Override solder mask expansion setting for pads in U4, so that this rule will be used. Remove manually placed soldermask cutouts in this part definition. * Shift TP14 to fix solder mask DRC error * Fix restring error with GND vias Addresses: https://osmocom.org/issues/5108 * Move 'stitching' gnd vias away from other vias, so that they do not violate the restring (annular ring) size limit on the GND plane layer. * Add a minimum annular ring DRC rule (which does not catch this kind of error, because the inner plane-style layers do not generate annular rings around connected vias).