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This repository has been archived by the owner on Aug 12, 2022. It is now read-only.

Issues: openpower-cores/a2i

13 Open 29 Closed
13 Open 29 Closed
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Issues list

Address space of an SoC using A2I core
#52 opened Jun 29, 2022 by Grubby-CPU
2
About some unknow instructions in A2 Core core RTL/Architecture documentation Improvements or additions to documentation
#51 opened Jun 8, 2022 by Grubby-CPU
2
Why msgclr does not set UsesSPR in iuq_fxu_decode.vhdl
#50 opened Apr 14, 2022 by Grubby-CPU
About the memory consistency model in A2
#49 opened Apr 10, 2022 by Grubby-CPU
Error happens when two threads co-execute together core RTL/Architecture
#47 opened Feb 28, 2022 by Grubby-CPU
16
Why choosing ex4 to deal with interrupt and exception core RTL/Architecture
#44 opened Oct 12, 2021 by Grubby-CPU
2
How to deal with wrong target address prediction of link stack core RTL/Architecture
#41 opened May 13, 2021 by Grubby-CPU
1
A design drawback of thread issue selection? core RTL/Architecture
#37 opened Nov 12, 2020 by zhaoxiahust
Any hints about the ignore_flush_is0 signal core RTL/Architecture
#33 opened Oct 29, 2020 by zhaoxiahust
1
Problem in simulation of the a2l2_axi.vhdl file core RTL/Architecture
#32 opened Oct 28, 2020 by xinyu8888
5
The RAW/WAW dependency check in iuq_fxu_dep.vhdl core RTL/Architecture
#29 opened Sep 10, 2020 by Grubby-CPU
1
Questions about the medium priority when selecting threads to issue core RTL/Architecture
#22 opened Sep 2, 2020 by Jackhuang-code
1
How to map the branch prediction algorithm to the RTL code core RTL/Architecture
#14 opened Aug 31, 2020 by Grubby-CPU
2
ProTip! Updated in the last three days: updated:>2024-11-24.