Skip to content

Tags: openhwgroup/corev-gcc

Tags

cv32e40pv2-release

Toggle cv32e40pv2-release's commit message
Update CORE-V documentation.

	* doc/extend.texi (CORE-V Builtin-in Functions): Rename as RISC-V
	(CORE-V), provide sub-subsection for the builtins for each ISA
	extension, present builtins as simple lists, reorder ISA
	extensions alphabetically.
	* doc/invoke.texi (RISC-V Options): Add missing CORE-V options for
	-march and order those options alphabetically.

Signed-off-by: Jeremy Bennett <[email protected]>